1. Field of the Invention
The present invention relates to a digital signal processing system which allows a high speed performance of compression of input speech data, that is, a low bit rate coding system, as well as relates an error correction coding system.
2. Description of the Related Arts
Shortage of radio frequency channels has become a serious problem caused by the increase in car telephones and portable telephones. Solution of the problem has been progressed by the employment of the digitalization technique and the compression technique. However, if it is attempted to solve the problem only by a software, i.e. by a firmware, the processing load becomes huge because the algorithm of the coding for decreasing the bit rate is complex and, accordingly, it is necessary to increase the memory capacity for the work area of the software. An expensive hardware, such as an efficient digital signal processor (DSP), is also needed therein for its real time processing.
On the other hand, portable equipments, such as portable telephones, are required to be small in size for the easy handling as well as to consume less power supplied from its battery in order to extend its operable period.
Various types of low bit rate coding methods have been already known to compress speech signals. For example, a vector quantizer as one of these low bit rate coding methods is such that: a code word is searched for to have a minimum residual power error of a difference between a speech input data and speech data synthesized with the linear predictive synthesis filter based on speech source data (code word) output from a codebook; then, the decrease of the bit rate is accomplished by synthesizing the speech according to the code data which minimizes the residual error power.
As for the vector quantizing method as the high efficiency low bit rate coding methods of speech signals, there have been employed a CELP (Code Excited Linear Prediction) coding method, an LD-CELP (Low Delay Code Excited Linear Prediction) coding method, and a VSELP (Vector Sum Excited Linear Prediction) coding method, etc.
In the vector quantizing method, plural word data in basic data groups are selected from the codebook as mentioned above corresponding to the input speech data so as to form a data array; speech data is synthesized with the linear predictive synthesis filter based on this data array; a residual power error of difference of the synthesized speech data and the input speech data is calculated; the residual power error data is calculated for each speech data synthesized according to the plural kinds of data arrays; then, a data array having a minimum residual power error is determined as the coded data. In this method, size of program to form the data arrays and to sort the data array that provides the minimum residual error power becomes comparatively large.
In this prior art method, the addresses to read the plural word data in the basic data groups of the codebook can be generated by the use of an address generating circuit in a processor such as digital signal processor (DSP) if the addresses change according to a simple rule. However, if the addresses of the individual word data composing the data array do not change in accordance with a simple rule, it is difficult to generate the addresses for reading the word data by the use of the address generating circuit of the processor. Therefore, the address generating operation must be performed by the use of operating function of the processor.
Algorithm of sorting processes, by which various data are compared, a maximum value or a minimum value is selected out of plural data, or a predetermined number of data are taken out in a descending order from the largest data or in an ascending order from the smallest data, have been already known. In performing these processes for plural operation results, it is usual that the operation results are once stored in a memory, and are read out of the memory after all the operation results are accomplished, for the comparison. That is, this kind of heavy processes must be performed even in a process to obtain a data array having a small residual error power.
In transmission lines where the transmission errors are apt to take place, such as radio channel, there has been employed a method to transmit the coded data in which the bit rate has been decreased by the low bit rate coding, by the use of convolution coding method according to a predetermined constraint length. In the receiver station, an error correction decoding is performed by a decoding means which employs a maximum likelihood decoding (decipherment) method such as Viterbi decoder. In such convolution coding system, there is provided a convolutional coding circuit which contains a shift register having its stages a quantity of which is in accordance with the constraint length.
Because in a prior art system the change of addresses in forming the data array by reading out plural word data out of the basic data groups in the codebook is comparatively complex, the address generating operation has been done by the operational function of the processor, that is, by a software. Therefore, there has been a problem in that the main data processing in the processor, such as the residual error power calculation, is restricted. There has been another problem in an increase in power consumption caused from an increase in processing cycles in the addressing operation, as well as in an increase in the memory capacity required for its work area, etc.
There has been still another problem in that the complex and large program is required in retrieving a predetermined number of the operation results, such as the residual power error of the difference between the input speech data and the synthesized speech data, in descending order from the maximum value, or in retrieving a predetermined number of the result data in ascending order from the minimum value; accordingly it is difficult to process the operation efficiently.
Convolution coding circuits correctly recover an erroneous signal by performing a convolution operation of a single bit of a serial input data and past plural bits. The convolution coding circuit includes a shift register by which the serial input data is shifted one by one, where it is difficult to observe the contents of the shift registers from its outside. Accordingly, it is difficult to check the match of the convolution operated results with the contents of the shift register. Thus, there is a problem in that it is not easy to check efficiently the convolution coding circuit. This is because an n-bit shift register having 2.sup.n kinds of its contents requires n cycles of the shifting operations; accordingly, nx2.sup.n cycles of the shift inputs are required in order to obtain the 2.sup.n kinds of the contents. Consequently, there is a problem in that it takes a long time in preparing test data necessary for verifying the convolution coding circuit and in verifying the convolution coding circuit.